我的芯片之路8

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上回说到测试环境的搭建

l 实验设备

逻辑分析仪

本机一台,ISE程序下载线

电流源一台

Xlinix FPGA virtex5一个

逻辑分析仪

我的芯片之路8

Virtex5 XC5VLX85 FPGA

 

我的芯片之路8

电压电流源

 

我的芯片之路8

 

联想笔记本一台。

软件环境:

Modelsim SE 10.2c

Xilinx ISE 14.7

(后记:测试果然是个天坑- -.迄今开始测试,[9月],至11月才完成

 

l ISE 的管脚约束

因为比较简单,没有用planahead(好啊主要是盗版可能老出问题就偷懒了)

.ucf写法见整理的【参考】ucf约束管脚写法

写成的.ucf文件如下

##CLK TO FPGA

NET “sha_clk” LOC = F8 | TNM_NET = sha_clk;

TIMESPEC TS_sha_clk = PERIOD “sha_clk” 30 ns HIGH 50 %;

##Reset Related Signals

NET”sha_reset_b” LOC =”AD26″; # RESET

NET “sha_reset_b” CLOCK_DEDICATED_ROUTE = FALSE;

##w_sha_wdata&sha_rdata

NET”w_sha_wdata[0]” LOC =”A24″;

NET”w_sha_wdata[1]” LOC =”A25″;

NET”w_sha_wdata[2]” LOC =”B25″;

NET”w_sha_wdata[3]” LOC =”D24″;

NET”w_sha_wdata[4]” LOC =”D25″;

NET”w_sha_wdata[5]” LOC =”E25″;

NET”w_sha_wdata[6]” LOC =”G26″;

NET”w_sha_wdata[7]” LOC =”H26″;

##PRE&ADDR

NET”w_sha_addr[0]” LOC =”B24″;

NET”w_sha_addr[1]” LOC =”B26″;

NET”w_sha_addr[2]” LOC =”C26″;

NET”w_sha_addr[3]” LOC =”D26″;

NET”w_sha_addr[4]” LOC =”E26″;

NET”w_pre[0]” LOC =”F25″;

NET”w_pre[1]” LOC =”G25″;

##OTHER CONTROL SIGNALS

NET”w_sha_ipen” LOC =”H24″;

NET”w_sha_rw_b” LOC =”J25″;

NET”w_sha_clk” LOC =”K25″;

NET”w_sha_reset_b” LOC =”M26″;

##STATE INDICATOR LED

NET”shastart_for_trigger” LOC =”AF5″;

NET”indicator_w32be_1″ LOC =”AD4″;

NET”indicator_w32_reuse” LOC =”AC4″;

NET”indicator_read_1″ LOC =”AD5″;

NET”indicator_read_reuse” LOC =”AB5″;

ü 需要注意NET “sha_reset_b” CLOCK_DEDICATED_ROUTE = FALSE;这句

不加的话,会引起 not using a Clock-IOB site to drive a global clock buffer.的错误

报错如下

Place:645 – A clock IOB clock component is not placed at an optimal clock

IOB site. The clock IOB component <sha_reset_b> is placed at site <AD26>. The

clock IO site can use the fast path between the IO and the Clock buffer/GCLK

if the IOB is placed in the master Clock IOB Site. If this sub optimal

condition is acceptable for this design, you may use the

CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a

WARNING and allow your design to continue. However, the use of this override

is highly discouraged as it may lead to very poor timing results. It is

recommended that this error condition be corrected in the design. A list of

all the COMP.PINs used in this clock placement rule is listed below. These

examples can be used directly in the .ucf file to override this clock rule.

< NET “sha_reset_b” CLOCK_DEDICATED_ROUTE = FALSE; >

问题解释

This error indicates that the design is not using a Clock-IOB site to drive a global clock buffer. Clock-IOB sites have a dedicated routing path to global buffers with reduced routing delay.
NOTE: The most common design mistake leading to this error results from a single-ended clock input being LOC’d to the N side of a differential pair of clock-capable I/O. Only the P side of the differential pair has the dedicated routing resource. When choosing a Global Clock IOB site, it is not enough to choose a site with “GC” in the pin definition. It is also necessary to choose the “P” side of a differential pair. For example, a pin definition of IO_L1P_GC_CC_LC_3 is valid as a Global Clock IOB site, whereas IO_L1N_GC_CC_LC_3 is not.
If the increased delay associated with the use of general routing resources is acceptable, the XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING environment variable can be set to reduce this error to a warning:
Windows
SET XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING=1
Linux and Solaris
setenv XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING 1
If this extra routing delay is not acceptable, the input should be constrained to a valid Clock-IOB site.
To check what type of I/O the Clock has been constrained to, refer to the Virtex-4 Packaging and Pinout Specification:
xilinx.com/xlnx/xweb/xi
Navigate to FPGA Device Families -> Virtex-4 -> Virtex-4 Packaging and Pinout Specification.
For more general information about setting ISE environment variables, see (Xilinx Answer 11630).
If the input in question is unconstrained, the error might be occurring because the design is infeasible from the Global Clock Component placement point of view. The placement of connected global clock components like Clock-IO, BUFGCTRL, DCM, PMCD, PLL and GT11CLK are governed by strict rules, all of which have to be simultaneously satisfied. Please refer to the Global Clocking Section of the User Guide for a complete list of all global clock placement rules.
It is also possible that PAR was unable to find a feasible placement solution when such a solution exists. You can help direct PAR to a good solution by LOCing the comps indicated in the error message to legal sites.

l ISE 的程序写入

知乎专栏【自制】ISE下载程序流程【ISE14.2】.docx

l 看懂开发板与开发板原理图

写入程序需要管脚分配,

管脚分配需要看开发板原理图

我的芯片之路8
我的芯片之路8

 

上表的FPGA管脚应该是.ucf分配的管脚名字,

具体我们看一下开发板的pcb文件

我的芯片之路8

 

Altium designer打开后,

原理图

这是个层级的pcb设计流程.

其实可以用来学习层级的原理图画法,参加’’altium designer 10电路设计标准教程的书的3-5章

Pcb图

我的芯片之路8
我的芯片之路8
我的芯片之路8
我的芯片之路8
我的芯片之路8

 

顺着板子,比如CN3的1pad,按照连线点到芯片的pad上,双击看到属性

可以看到,designator上写着A17,IO_100

和表对应

我的芯片之路8

 

后记:测试最初的结果很是诡异.也很零散,这个芯片远远超过了我们预想的可能出现的结果.

能把数字芯片做成这样,…也是醉了…

我想把测试过程中间的一些考虑,一些矛盾和迷茫记录下来但是发现过于琐碎,没有线穿起来..

中间老师给了我很多思路让我可以继续测下去…

直接写上一些结论和通用方法吧,测试这个东西主要是测出对的部分,只要结果对一次就有模块能对,但是证明错误很难.

写明测试过程还需要整理SHA算法,思路很麻烦,而且这主要是个经验的问题,需要积累。就不赘述了

常用的测试方法:

² 提高电压

² 降低频率

² 看pcb/版图,万用表测测管脚短没短之类的

² 分开步骤,单步骤步骤的看波形

² 试试全0,全1这种有可能结果会暴露出一定问题的输入

² 试着引出内部信号可以测试

至此,回所后的第一个任务结束了。

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微博@georgeuser,一枚很可能要搞硬件的喵控的专业记录日记。

记录我所走过的路,愿我的分享能予人一些借鉴,也愿我某日再回头时能再拾起细节。