我的芯片之路6

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我的芯片之路6

上回说到将进行modelsim和ISE的联合仿真

l 联合后仿设置

挺麻烦的,而且版本不一,我用的是modelsim se-10c 和ISE 14.7

详情见本专栏内的 【备忘】ISE与Modelsim进行FPGA后仿真,【备忘】ISE与Modelsim进行FPGA后仿真 – 我的芯片之路 – 知乎专栏

l 我的后仿代码

版本sha_syn7_20160905(附tb代码):

`timescale 10ns/1ps

module sha_state_tb;

parameter S0=3’b000,

S1=3’b001,

S2=3’b010,

S3=3’b011,

S4=3’b100,

S5=3’b101;

// reg [7:0]w_sha_wdata;

// reg [4:0]w_sha_addr;

// reg [1:0]w_pre;

reg sha_clk ;

reg sha_reset_b ;

wire [7:0] sha_rdata ;

wire [1:0]w_pre;

wire [4:0] w_sha_addr;

wire w_sha_rw_b,w_sha_ipen;

wire [7:0]w_sha_wdata;

/*

reg [7:0] sha_wdata ;

reg sha_rw_b ;

reg [4:0] sha_addr ;

reg [1:0] pre ;

reg sha_ipen ;

*/

sha_state

sha_state(

.sha_clk (sha_clk ) ,

.sha_reset_b (sha_reset_b ),

.w_sha_wdata(w_sha_wdata),

.w_sha_rw_b(w_sha_rw_b),

.w_sha_ipen(w_sha_ipen),

.w_sha_addr(w_sha_addr),

.w_pre(w_pre),

.sha_rdata(sha_rdata));

/*

sha_state

DUT(

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ));

*/

/* .delaystart(delaystart), 搴旇涓嶇敤缁欒鏁板櫒鐨勬帶鍒朵俊鍙凤紝鍦╯ha_state module涓嚜宸卞畾涔 .delaystop(delaystop),

.delay(delay));

*/

initial begin

sha_clk = 1’b0;

forever

#1 sha_clk = ~sha_clk ;

end

initial begin

sha_reset_b=1’b1;

#25 sha_reset_b=1’b0;

#25 sha_reset_b=1’b0;

#25 sha_reset_b=1’b1;

end

endmodule

/*module閲岄潰+start锛宻top锛宒elay淇″彿

瀹炰緥鍖栦竴涓猚ounter锛堣鏁板櫒锛夊仛寤舵椂锛屼笉搴旇姣忔鐢ㄥ畠鏃堕兘鍘诲疄渚嬪寲= =

*/

module sha_state(sha_clk , sha_reset_b ,w_sha_wdata,w_sha_rw_b,w_sha_ipen,w_sha_addr,w_pre,sha_rdata);

parameter SHACTRL=5’b01000,

SHADI0=5’b10000,

SHADI1=5’b10001,

SHADI2=5’b10010,

SHADI3=5’b10011,

SHADI4=5’b10100,

SHADI5=5’b10101,

SHADI6=5’b10110,

SHADI7=5’b10111,

SHADI8=5’b11000,

SHADI9=5’b11001,

SHADIA=5’b11010,

SHADIB=5’b11011,

SHADIC=5’b11100,

SHADID=5’b11101,

SHADIE=5’b11110,

SHADIF=5’b11111,

SHADO0=5’b00000,

SHADO1=5’b00001,

SHADO2=5’b00010,

SHADO3=5’b00011,

SHADO4=5’b00100,

SHADO5=5’b00101,

SHADO6=5’b00110,

SHADO7=5’b00111;

parameter

S4_1=5’b00000,

S4_1_2=5’b00001,

S4_2=5’b00010,

S4_2_2=5’b00011,

S4_3=5’b00100,

S4_3_2=5’b00101,

S4_4=5’b00110,

S4_4_2=5’b00111,

S4_5=5’b01000,

S4_5_2=5’b01001,

S4_6=5’b01010,

S4_6_2=5’b01011,

S4_7=5’b01100,

S4_7_2=5’b01101,

S4_8=5’b01110,

S4_8_2=5’b01111,

S4_9=5’b10000,

S4_9_2=5’b10001,

S4_10=5’b10010,

S4_10_2=5’b10011,

S4_11=5’b10100,

S4_11_2=5’b10101,

S4_12=5’b10110,

S4_12_2=5’b10111,

S4_13=5’b11000,

S4_13_2=5’b11001,

S4_14=5’b11010,

S4_14_2=5’b11011,

S4_15=5’b11100,

S4_15_2=5’b11101,

S4_16=5’b11110,

S4_16_2=5’b11111;

parameter S0=3’b000,

S1=3’b001,

S2=3’b010,

S3=3’b011,

S4=3’b100,

S5=3’b101,

S6=3’b110,

S7=3’b111;

input sha_clk , sha_reset_b ;

output wire [7:0]sha_rdata;

output wire [7:0]w_sha_wdata;

output wire w_sha_rw_b,w_sha_ipen;

output wire [4:0] w_sha_addr;

output wire [1:0] w_pre ;

reg sha_rw_b,sha_ipen;

reg [7:0] sha_wdata ;

reg [4:0] sha_addr ;

reg [1:0] pre ;

assign w_sha_wdata=sha_wdata;

assign w_sha_rw_b=sha_rw_b;

assign w_sha_ipen=sha_ipen;

assign w_sha_addr=sha_addr;

assign w_pre=pre;

/*

reg [7:0] sha_wdata ;

reg sha_rw_b ;

reg [4:0] sha_addr ;

reg [1:0] pre ;

reg sha_ipen;

*/

reg [2:0]current_state;

reg [4:0]S4_state;

reg startS1;

reg startS2;

reg startS3;

reg startS4;

reg startS5;

reg startS6;

reg sign0;

reg sign1;

reg sign2;

reg sign2_0;

reg sign2_1;

reg sign2_2;

reg sign3_0;

reg sign3_1;

reg sign3_2;

reg sign3_3;

reg sign3_4;

reg sign3_5;

reg sign3_6;

reg sign3_7;

reg sign3_8;

reg sign5_0;

reg sign6_delay;

reg sign6_0;

reg sign6_1;

reg sign6_2;

reg sign6_3;

reg sign6_4;

reg sign6_5;

reg sign6_6;

reg sign6_7;

reg sign6_8;

/*

sha_iptop

CORE (

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ) );

*/

//counter瀹炰緥鍖

reg counter_start;

reg [15:0]delay;

reg counter_reset;

wire counter_stop;//counter鐨勮繑鍥炲€艰鏀逛负wire

wire counter_reuse;

counter c0(.clk(sha_clk),

.rst(counter_reset),

.start(counter_start),

.delay(delay),

.stop(counter_stop),

.reuse(counter_reuse));

//W32be瀹炰緥鍖

reg w32be_start;

reg w32be_reset;

reg [31:0]w32be_data;

reg [4:0]w32be_addr;

wire [7:0]w32be_sha_wdata;

wire [1:0]w32be_pre;

wire w32be_stop;

// wire w32be_reuse;

wire w32be_reuse;

assign w32be_reuse=~w32be_reset;

W32be W32be(

.clk(sha_clk),

.rst(w32be_reset),

.start(w32be_start),

.addr(w32be_addr),

.data(w32be_data),

.pre(w32be_pre),

.sha_wdata(w32be_sha_wdata),

.stop(w32be_stop),

.reuse(w32be_reuse));

//read瀹炰緥鍖

reg read_start;

reg read_reset;

reg [4:0]read_addr;

wire [1:0]read_pre;

wire read_stop;

wire read_reuse;

assign read_reuse=~read_reset;

// wire read_reuse;

read read(

.clk(sha_clk),

.rst(read_reset),

.start(read_start),

.addr(read_addr),

.pre(read_pre),

.stop(read_stop),

.reuse(read_reuse));

always@(posedge sha_clk)

if(sha_reset_b == 1’b0)

begin

current_state=S0;

end

else

begin

case(current_state)

S0:begin

sha_ipen=1’b0;

sha_rw_b=1’b1;

sha_wdata=8’b0;

sha_addr =5’b00000;

pre=2’b00;

counter_start=1’b0;

delay=0;

startS1=1’b0;

current_state=S1;

w32be_reset=0;

read_reset=0;

S4_state=5’b00000;

startS1=1’b0;

startS2=1’b0;

startS3=1’b0;

startS4=1’b0;

startS5=1’b0;

startS6=1’b0;

sign0=1’b0;

sign1=1’b0;

sign2=1’b0;

sign2_0=1’b0;

sign2_1=1’b0;

sign2_2=1’b0;

sign3_0=1’b0;

sign3_1=1’b0;

sign3_2=1’b0;

sign3_3=1’b0;

sign3_4=1’b0;

sign3_5=1’b0;

sign3_6=1’b0;

sign3_7=1’b0;

sign3_8=1’b0;

sign5_0=1’b0;

sign6_delay=1’b0;

sign6_0=1’b0;

sign6_1=1’b0;

sign6_2=1’b0;

sign6_3=1’b0;

sign6_4=1’b0;

sign6_5=1’b0;

sign6_6=1’b0;

sign6_7=1’b0;

sign6_8=1’b0;

end

S1:begin

if(startS1==1’b0)

begin

counter_start =1’b1;

delay =16’h0020;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h1101;

startS1=1’b1;

sign0=1’b1;

counter_reset=1;

end

end

//淇″彿sign0锛屽搴#500 sha_ipen=1’b1;

else if(sign0==1’b1)

begin

counter_reset=0;//=1鏃秗eset

begin

counter_start=1’b1;

delay=16’h0019;//#50

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h1102;

sha_ipen=1’b1;

sign0=1’b0;

sign1=1’b1;

counter_reset=1;

end

end

end

//淇″彿sign1锛屽搴500

else if(sign1==1’b1)

begin

counter_reset=0;

begin

counter_start=1’b1;

delay=16’h0019;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h1103;

sign1=1’b0;

current_state=S2;

counter_reset=1;

end

end

end

end

// S2:W32be(SHACTRL,32’h0000000a);#8000;

S2:begin

if(startS2==1’b0)

begin

assign pre=w32be_pre;

assign sha_wdata=w32be_sha_wdata;

sha_addr=SHACTRL;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_reset=1;

w32be_data=32’h0000000a;

// w32be_addr=SHACTRL;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

startS2=1’b1;

sign2_0=1’b1;

w32be_reset=0;

end

end

else if(sign2_0==1’b1)

begin

w32be_reset=1;

sign2_0=0;

sign2_1=1;

deassign pre;

deassign sha_wdata;

end

//淇″彿sign2_1锛屽搴#8000

else if(sign2_1==1’b1)

begin

counter_reset=0;//=1鏃秗eset

begin

counter_start=1’b1;

delay=16’h0190;//#400;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h2200;

sign2_1=1’b0;

sign2_2=1’b1;

current_state=S3;

counter_reset=1;

end

end

end

end

S3:begin

//read(SHACTRL);

if(startS3==1’b0)

begin

assign pre=read_pre;

sha_rw_b=1’b1;

read_start=1’b1;

read_reset=1;

sha_addr=SHACTRL;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

startS3=1’b1;

sign3_0=1’b1;

read_reset=0;

end

end

// read(SHADO0);

else if(sign3_0==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO0;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_0=1’b0;

sign3_1=1’b1;

read_reset=0;

end

end

end

// read(SHADO1);

else if(sign3_1==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO1;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_1=1’b0;

sign3_2=1’b1;

read_reset=0;

end

end

end

// read(SHADO2);

else if(sign3_2==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO2;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_2=1’b0;

sign3_3=1’b1;

read_reset=0;

end

end

end

// read(SHADO3);

else if(sign3_3==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO3;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_3=1’b0;

sign3_4=1’b1;

read_reset=0;

end

end

end

// read(SHADO4);

else if(sign3_4==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO4;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_4=1’b0;

sign3_5=1’b1;

read_reset=0;

end

end

end

// read(SHADO5);

else if(sign3_5==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO5;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_5=1’b0;

sign3_6=1’b1;

read_reset=0;

end

end

end

// read(SHADO6);

else if(sign3_6==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO6;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_6=1’b0;

sign3_7=1’b1;

read_reset=0;

end

end

end

// read(SHADO7);

else if(sign3_7==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO7;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign3_7=1’b0;

sign3_8=1’b1;

current_state=S4;

deassign pre;

read_reset=0;

end

end

end

end

S4:

begin

if(startS4==1’b0)

begin

assign pre=w32be_pre;

assign sha_wdata=w32be_sha_wdata;

sha_rw_b=1’b1;

case(S4_state)

//W32(SHADI0,32’h61626364);

S4_1:

begin

sha_addr=SHADI0;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_reset=1;

w32be_data=32’h61626364;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_1_2;

end

end

S4_1_2: // #100 sha_rw_b=1’b1;

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_2;

counter_reset=1;

end

end

// W32(SHADI1,32’h62636465);#100 sha_rw_b=1’b1;

S4_2:

begin

w32be_reset=1;

sha_addr=SHADI1;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h62636465;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_2_2;

end

end

S4_2_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_3;

counter_reset=1;

end

end

// W32(SHADI2,32’h63646566);

S4_3:

begin

w32be_reset=1;

sha_addr=SHADI2;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h63646566;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_3_2;

end

end

S4_3_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_4;

counter_reset=1;

end

end

// W32(SHADI3,32’h64656667);

S4_4:

begin

w32be_reset=1;

sha_addr=SHADI3;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h64656667;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_4_2;

end

end

S4_4_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_5;

counter_reset=1;

end

end

// W32(SHADI4,32’h65666768);

S4_5:

begin

w32be_reset=1;

sha_addr=SHADI4;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h65666768;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_5_2;

end

end

S4_5_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_6;

counter_reset=1;

end

end

//寮€濮嬪鍒W32(SHADI5,32’h66676869);

S4_6:

begin

w32be_reset=1;

sha_addr=SHADI5;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h66676869;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_6_2;

end

end

S4_6_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_7;

counter_reset=1;

end

end

// W32(SHADI6,32’h6768696a);//read(SHADI6);

S4_7:

begin

w32be_reset=1;

sha_addr=SHADI6;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6768696a;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_7_2;

end

end

S4_7_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_8;

counter_reset=1;

end

end

S4_8:

begin

w32be_reset=1;

sha_addr=SHADI7;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h68696a6b;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_8_2;

end

end

S4_8_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_9;

counter_reset=1;

end

end

//W32(SHADI8,32’h696a6b6c);//read(SHADI8);

S4_9:

begin

w32be_reset=1;

sha_addr=SHADI8;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h696a6b6c;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_9_2;

end

end

S4_9_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_10;

counter_reset=1;

end

end

// W32(SHADI9,32’h6a6b6c6d);//read(SHADI9);

S4_10:

begin

w32be_reset=1;

sha_addr=SHADI9;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6a6b6c6d;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_10_2;

end

end

S4_10_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_11;

counter_reset=1;

end

end

// W32(SHADIA,32’h6b6c6d6e);//read(SHADIA);

S4_11:

begin

w32be_reset=1;

sha_addr=SHADIA;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6b6c6d6e;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_11_2;

end

end

S4_11_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_12;

counter_reset=1;

end

end

// W32(SHADIB,32’h6c6d6e6f);//read(SHADIB);

S4_12:

begin

w32be_reset=1;

sha_addr=SHADIB;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6c6d6e6f;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_12_2;

end

end

S4_12_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_13;

counter_reset=1;

end

end

// W32(SHADIC,32’h6d6e6f70);//read(SHADIC);

S4_13:

begin

w32be_reset=1;

sha_addr=SHADIC;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6d6e6f70;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_13_2;

end

end

S4_13_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_14;

counter_reset=1;

end

end

// W32(SHADID,32’h6e6f7071);//read(SHADID);

S4_14:

begin

w32be_reset=1;

sha_addr=SHADID;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6e6f7071;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_14_2;

end

end

S4_14_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_15;

counter_reset=1;

end

end

// W32(SHADIE,32’h80000000);//read(SHADIE);

S4_15:

begin

w32be_reset=1;

sha_addr=SHADIE;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h80000000;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_15_2;

end

end

S4_15_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

S4_state = S4_16;

counter_reset=1;

end

end

// W32(SHADIF,32’h00000000);//read(SHADIF);

S4_16:

begin

w32be_reset=1;

sha_addr=SHADIF;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h00000000;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

S4_state=S4_16_2;

end

end

S4_16_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h8888;//闅忎究涓€涓爣绀

sha_rw_b=1’b1;

//缁撴潫淇″彿

S4_state = S4_16_2;

startS4=1;

current_state=S5;

deassign pre;

deassign sha_wdata;

counter_reset=1;

end

end

endcase

end

end

S5:

begin

if(startS5==1’b0)

begin

counter_reset=0;

counter_start =1’b1;

delay =16’h0032;//#1000ns,50涓懆鏈 if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h9999;

startS5=1’b1;

sign5_0=1’b1;

counter_reset=1;

end

end

//W32(SHACTRL,32’h00000009);

else if(sign5_0==1’b1)

begin

assign pre=w32be_pre;

assign sha_wdata=w32be_sha_wdata;

sha_rw_b=1’b1;

w32be_reset=1;

sha_addr=SHACTRL;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h00000009;

if(w32be_stop==1)//瀹屾垚寤舵椂

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//鎺у埗鍏抽棴淇″彿

w32be_reset=0;

deassign pre;

deassign sha_wdata;

sign5_0=1’b0;

current_state=S6;

end

end

end

S6:

begin

//read(SHACTRL);

if(startS6==1’b0)

begin

assign pre=read_pre;

sha_rw_b=1’b1;

read_reset=1;

read_start=1’b1;

sha_addr=SHACTRL;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

startS6=1’b1;

sign6_delay=1’b1;

read_reset=0;

// sha_rw_b=1’b0;

end

end

//#14000

if(sign6_delay==1’b1)

begin

counter_reset=0;

counter_start =1’b1;

delay =16’h02bc;//#14000ns,700涓懆鏈

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start=1’b0;

delay=16’h9988;

sign6_delay=1’b0;

sign6_0=1’b1;

counter_reset=1;

end

end

// read(SHADO0);

else if(sign6_0==1’b1)

begin

read_reset=1;//=1鏃秗eset

// sha_rw_b=1’b1;

begin

read_start=1’b1;

sha_addr=SHADO0;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_0=1’b0;

sign6_1=1’b1;

read_reset=0;

// sha_rw_b=1’b0;

end

end

end

// read(SHADO1);

else if(sign6_1==1’b1)

begin

read_reset=1;//=1鏃秗eset

// sha_rw_b=1’b1;

begin

read_start=1’b1;

sha_addr=SHADO1;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_1=1’b0;

sign6_2=1’b1;

read_reset=0;

// sha_rw_b=1’b0;

end

end

end

// read(SHADO2);

else if(sign6_2==1’b1)

begin

read_reset=1;//=1鏃秗eset

// sha_rw_b=1’b1;

begin

read_start=1’b1;

sha_addr=SHADO2;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_2=1’b0;

sign6_3=1’b1;

read_reset=0;

// sha_rw_b=1’b0;

end

end

end

// read(SHADO3);

else if(sign6_3==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO3;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_3=1’b0;

sign6_4=1’b1;

read_reset=0;

end

end

end

// read(SHADO4);

else if(sign6_4==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO4;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_4=1’b0;

sign6_5=1’b1;

read_reset=0;

end

end

end

// read(SHADO5);

else if(sign6_5==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO5;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_5=1’b0;

sign6_6=1’b1;

read_reset=0;

end

end

end

// read(SHADO6);

else if(sign6_6==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO6;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_6=1’b0;

sign6_7=1’b1;

read_reset=0;

end

end

end

// read(SHADO7);

else if(sign6_7==1’b1)

begin

read_reset=1;//=1鏃秗eset

begin

read_start=1’b1;

sha_addr=SHADO7;

read_addr=sha_addr;

if(read_stop==1)//瀹屾垚寤舵椂

begin

read_start=1’b0;

sign6_7=1’b0;

sign6_8=1’b1;

current_state=S7;

deassign pre;

read_reset=0;

end

end

end

end

S7:

begin

end

endcase

end

endmodule

module counter(clk,rst,start,delay,stop,reuse);//delay猫庐隆忙聲掳氓聶篓茂录聦rst忙颅拢氓赂赂盲赂聥=0茂录聦盲赂潞1茅聡聧莽陆庐盲陆聧茂录聦//start=1忙聴露氓聬炉氓聤篓//stop=1忙聴露莽禄聯忙聺聼茂录聦

input clk,rst;

input start;

input [15:0] delay;//delay忙聲掳忙聧庐

// input delay;

output wire stop;//stop=1鏃讹紝鏈璁℃椂缁撴潫

output wire reuse;//resure=1鏃讹紝鍙互寮€濮嬩笅涓€娆¤鏁板懆鏈

reg [15:0] counter=16’h0;

reg stop_reg=1’b0;

reg reuse_reg=1’b0;

reg [1:0] state=2’b00;

assign stop = stop_reg;

assign reuse = reuse_reg;

always @ (posedge clk or posedge rst)//rst猫驴聶盲赂陋茅隆鹿莽聸庐莽聰篓盲赂聧盲赂聤茫聙聜茫聙聜

begin

if (rst)//rst=1莽陆庐盲陆聧茫聙聜忙颅拢氓赂赂盲赂聥rst=0

begin

counter <= 16’h0;

stop_reg <= 1’b0;

reuse_reg<= 1’b1;

state <= 2’b00;

end

else

case(state)

2’b00:

begin

stop_reg <=1’b0;

reuse_reg<=1’b1;

if(start == 1’b1)

begin

state <= 2’b01;

reuse_reg <=1’b0;

end

else

begin

stop_reg <=1’b0;//stop=1忙聴露氓聛聹忙颅垄茂录聦stop=0莽禄搂莽禄颅

reuse_reg<=1’b1;

end

end

2’b01:

begin

counter <= counter + 1;

if(counter==delay)

begin

stop_reg <= 1’b1;//猫庐隆忙聲掳氓庐聦忙炉聲茫聙聜stop_reg=1

state <= 2’b10;

counter <=16’h0;

end

end

2’b10:

begin

// state <= 2’b11;

state <=2’b00;

end

endcase

end

endmodule

module W32be(clk,rst,start,addr,data,pre,sha_wdata,stop,reuse);//delay猫庐隆忙聲掳氓聶篓茂录聦rst忙颅拢氓赂赂盲赂聥=0茂录聦盲赂潞1茅聡聧莽陆庐盲陆聧茂录聦//start=1忙聴露氓聬炉氓聤篓//stop=1忙聴露莽禄聯忙聺聼茂录聦

input clk,rst;//clk鏄粰counter鐢ㄧ殑銆俽st鏄嚜宸辩敤鐨勶紝鍦╯tate.v涓璵odule state涓皟鐢ㄥ鐢

input start;

input [4:0] addr;

input [31:0] data;

input reuse;

//output,澶嶇敤閮ㄥ垎淇″彿

output wire stop;//stop=1鏃讹紝鏈璁℃椂缁撴潫

reg stop_reg;

assign stop = stop_reg;

//output锛屾甯哥殑淇″彿鎺у埗閮ㄥ垎

output wire [1:0]pre;

output wire [7:0]sha_wdata;

reg [1:0]pre_reg;

reg [7:0]sha_wdata_reg;

assign pre=pre_reg;

assign sha_wdata=sha_wdata_reg;

//缁檆ounter鐨勬帶鍒朵俊鍙

reg counter_start;

reg [15:0]counter_delay;

reg counter_reset;

wire counter_stop;

wire counter_reuse;

//鐘舵€佷俊鍙

reg sign0;

reg sign1;

reg sign2;

reg sign3;

reg sign4;

reg sign5;

reg [2:0] state;

counter w0(.clk(clk),//璇籹top锛宻top=1鏃剁粨鏉

.rst(counter_reset),

.start(counter_start),

.delay(counter_delay),

.stop(counter_stop),

.reuse(counter_reuse));

always @ (posedge clk or negedge rst )//or negedge reuse )//rst猫驴聶盲赂陋茅隆鹿莽聸庐莽聰篓盲赂聧盲赂聤茫聙聜茫聙聜

begin

if (!rst)//rst=1莽陆庐盲陆聧茫聙聜忙颅拢氓赂赂盲赂聥rst=0

begin

counter_reset<=1;

stop_reg <= 1’b0;

state <= 3’b000;

counter_start<=0;

sign0<=1’b0;

sign1<=1’b0;

sign2<=1’b0;

sign3<=1’b0;

sign4<=1’b0;

sign5<=1’b0;

end

else

begin

case(state)

3’b000:

begin

counter_reset<=0;

stop_reg <=1’b0;

pre_reg<=2’b00;//这个是比较精髓的,不加在rst信号里,保证pre和addr的同时改变

if(start == 1’b1)

begin

state <= 3’b001;

sign0<=1;

end

else

begin

state <= 3’b000;

end

end

3’b001:

begin

//#100; pre=adr; sha_wdata=data;

if(sign0==1’b1)

begin

counter_start<=1’b1;

counter_delay<=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h3201;//闅忎究涓€涓爣绀

pre_reg<=2’b00;

sha_wdata_reg<=data[7:0];

sign0<=1’b0;

sign1<=1’b1;

state <= 3’b010;

counter_reset<=1;

end

end

end

3’b010:

begin

//#100; pre=adr; sha_wdata=data;

if(sign1==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h3302;//闅忎究涓€涓爣绀

pre_reg<=2’b01;

sha_wdata_reg<=data[15:8];

sign1<=1’b0;

sign2<=1’b1;

counter_reset<=1;

state <= 3’b011;

end

end

end

end

3’b011:

begin

//#100; pre=adr; sha_wdata=data;

if(sign2==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h3203;//闅忎究涓€涓爣绀

pre_reg<=2’b10;

sha_wdata_reg<=data[23:16];

sign2<=1’b0;

sign3<=1’b1;

counter_reset<=1;

state <= 3’b100;

end

end

end

end

3’b100:

begin

//#100; pre=adr; sha_wdata=data;

if(sign3==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h3204;//闅忎究涓€涓爣绀

pre_reg<=2’b11;

sha_wdata_reg<=data[31:24];

sign3<=1’b0;

sign4<=1’b1;

counter_reset<=1;

state <= 3’b101;

end

end

end

end

3’b101:

begin

//#100; sha_rw_b=1’b0;(杩欎釜鏀逛氦缁檓odule state鎺у埗锛屽湪杩愯w32be缁撴潫鍚 sha_addr=adr;(杩欎釜涓嶇敤浜

if(sign4==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h3232;//闅忎究涓€涓爣绀

sign4<=1’b0;

sign5<=1’b1;

counter_reset<=1;

state <= 3’b110;

end

end

end

end

3’b110:

begin

state <=3’b111;

stop_reg <= 1’b1;

end

3’b111:

begin

state <=3’b000;

end

endcase

end

end

endmodule

module read(clk,rst,start,addr,pre,stop,reuse);//delay猫庐隆忙聲掳氓聶篓茂录聦rst忙颅拢氓赂赂盲赂聥=0茂录聦盲赂潞1茅聡聧莽陆庐盲陆聧茂录聦//start=1忙聴露氓聬炉氓聤篓//stop=1忙聴露莽禄聯忙聺聼茂录聦

input clk,rst,reuse;//clk鏄嚜宸辩敤&缁檆ounter鐢ㄧ殑銆俽st鏄嚜宸辩敤鐨勶紝鍦╯tate.v涓璵odule state涓皟鐢ㄥ鐢

input start;

input [4:0] addr;

//output,澶嶇敤閮ㄥ垎淇″彿

output wire stop;//stop=1鏃讹紝鏈璁℃椂缁撴潫

reg stop_reg;

assign stop = stop_reg;

//output锛屾甯哥殑淇″彿鎺у埗閮ㄥ垎

output wire [1:0]pre;

reg [1:0]pre_reg;

assign pre=pre_reg;

//缁檆ounter鐨勬帶鍒朵俊鍙

reg counter_start;

reg [15:0]counter_delay;

reg counter_reset;

wire counter_stop;

wire counter_reuse;

//鐘舵€佷俊鍙

reg sign0;

reg sign1;

reg sign2;

reg sign3;

reg sign4;

reg sign5;

reg [2:0] state;

counter r0(.clk(clk),//璇籹top锛宻top=1鏃剁粨鏉

.rst(counter_reset),

.start(counter_start),

.delay(counter_delay),

.stop(counter_stop),

.reuse(counter_reuse));

//浠庤繖寮€濮嬫敼20160817

always @ (negedge clk or negedge rst)//修改成功。和主程序&w32beclk不一致,且reset从0-1时时序比较严格,要求addr和pre同时改变

begin

if (!rst)

begin

state <= 3’b000;

stop_reg <= 1’b0;

counter_reset<=1;

counter_start<=0;

sign0<=1’b0;

sign1<=1’b0;

sign2<=1’b0;

sign3<=1’b0;

sign4<=1’b0;

sign5<=1’b0;

end

else

begin

case(state)

3’b000:

begin

counter_reset<=0;

stop_reg<=1’b0;

pre_reg<=2’b00;

// stop_reg <= 1’b0;

//

counter_start<=0;

sign0<=1’b0;

sign1<=1’b0;

sign2<=1’b0;

sign3<=1’b0;

sign4<=1’b0;

sign5<=1’b0;

if(start == 1’b1)

begin

state <= 3’b001;

sign0<=1;

end

else

begin

state <= 3’b000;

end

end

3’b001:

begin

//#100; sha_addr=addr; pre=2’b00;

if(sign0==1’b1)

begin

counter_start<=1’b1;

counter_delay<=10;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h4401;//闅忎究涓€涓爣绀

pre_reg<=2’b00;

sign0<=1’b0;

sign1<=1’b1;

state <= 3’b010;

counter_reset<=1;

end

end

end

3’b010:

begin

//#200; pre=2’b01;

if(sign1==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=10;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h4402;//闅忎究涓€涓爣绀

pre_reg<=2’b01;

sign1<=1’b0;

sign2<=1’b1;

counter_reset<=1;

state <= 3’b011;

end

end

end

end

3’b011:

begin

// #200 pre=2’b10;//鈥01鐘舵€

if(sign2==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=10;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h4403;//闅忎究涓€涓爣绀

pre_reg<=2’b10;

sign2<=1’b0;

sign3<=1’b1;

counter_reset<=1;

state <= 3’b100;

end

end

end

end

3’b100:

begin

// #200 pre=2’b11;

if(sign3==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=5;

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h4404;//闅忎究涓€涓爣绀

pre_reg<=2’b11;

sign3<=1’b0;

sign4<=1’b1;

counter_reset<=1;

state <= 3’b101;

end

end

end

end

3’b101:

begin

//#200;

if(sign4==1’b1)

begin

counter_reset<=0;//=1鏃秗eset

begin

counter_start<=1’b1;

counter_delay<=5;//change to #100

if(counter_stop==1)//瀹屾垚寤舵椂

begin

counter_start<=1’b0;

counter_delay<=16’h4405;//闅忎究涓€涓爣绀

sign4<=1’b0;

sign5<=1’b1;

counter_reset<=1;

state <= 3’b110;

end

end

end

end

3’b110:

begin

state<=3’b111;

stop_reg <= 1’b1;

counter_reset<=1;

end

3’b111:

begin

state <=3’b000;

end

endcase

end

end

endmodule

(后记:很多还是不完善的地方,这个版本可以过综合这点我确定)

下期将开始画测试用pcb底板,将芯片插在上面进行最终实物测试

——————————–

微博@georgeuser,一枚很可能要搞硬件的喵控的专业记录日记。

记录我所走过的路,愿我的分享能予人一些借鉴,也愿我某日再回头时能再拾起细节。