我的芯片之路4

admin发布

我的芯片之路4

上回说到将完成前仿

*************

建议把这篇的代码复制到notepad++等代码文本编辑器里面。。。存为.v文件容易看。。。。。

部分注释都是没有改的。。。。读者见谅了。。。

*************

l

我的芯片之路4

通过前仿的代码

一共的文件如上图。

scll40nll_hs_wd_lvt_tt_v1p1_25c_ccs

sha_iptop_post

为工艺文件、综合后的芯片文件,是要测试的内核(大概这意思)

Sha_state为主流程

module sha_state(sha_clk , sha_reset_b ,sha_rdata,monitor1,monitor2,monitor3);

parameter SHACTRL=5’b01000,

SHADI0=5’b10000,

SHADI1=5’b10001,

SHADI2=5’b10010,

SHADI3=5’b10011,

SHADI4=5’b10100,

SHADI5=5’b10101,

SHADI6=5’b10110,

SHADI7=5’b10111,

SHADI8=5’b11000,

SHADI9=5’b11001,

SHADIA=5’b11010,

SHADIB=5’b11011,

SHADIC=5’b11100,

SHADID=5’b11101,

SHADIE=5’b11110,

SHADIF=5’b11111,

SHADO0=5’b00000,

SHADO1=5’b00001,

SHADO2=5’b00010,

SHADO3=5’b00011,

SHADO4=5’b00100,

SHADO5=5’b00101,

SHADO6=5’b00110,

SHADO7=5’b00111;

parameter

S4_1=5’b00000,

S4_1_2=5’b00001,

S4_2=5’b00010,

S4_2_2=5’b00011,

S4_3=5’b00100,

S4_3_2=5’b00101,

S4_4=5’b00110,

S4_4_2=5’b00111,

S4_5=5’b01000,

S4_5_2=5’b01001,

S4_6=5’b01010,

S4_6_2=5’b01011,

S4_7=5’b01100,

S4_7_2=5’b01101,

S4_8=5’b01110,

S4_8_2=5’b01111,

S4_9=5’b10000,

S4_9_2=5’b10001,

S4_10=5’b10010,

S4_10_2=5’b10011,

S4_11=5’b10100,

S4_11_2=5’b10101,

S4_12=5’b10110,

S4_12_2=5’b10111,

S4_13=5’b11000,

S4_13_2=5’b11001,

S4_14=5’b11010,

S4_14_2=5’b11011,

S4_15=5’b11100,

S4_15_2=5’b11101,

S4_16=5’b11110,

S4_16_2=5’b11111;

parameter S0=3’b000,

S1=3’b001,

S2=3’b010,

S3=3’b011,

S4=3’b100,

S5=3’b101,

S6=3’b110,

S7=3’b111;

input sha_clk , sha_reset_b ;

output wire [7:0]sha_rdata;

//reg [7:0] sha_rdata_reg;

//assign sha_rdata = sha_rdata_reg;

output monitor1,monitor2,monitor3;

reg [7:0] sha_wdata=8’b0 ;

reg sha_rw_b = 1’b1 ;

reg [4:0] sha_addr =5’b00000 ;

reg [1:0] pre =2’b00 ;

reg sha_ipen=1’b0 ;

//状态信号

reg [2:0]current_state=3’b000;

reg [4:0]S4_state=5’b000;

//测试用

reg monitor1_reg=1’b0;

reg monitor2_reg=1’b0;

reg monitor3_reg=1’b0;

assign monitor1=monitor1_reg;

assign monitor2=monitor2_reg;

assign monitor3=monitor3_reg;

*/

reg startS1=1’b0;

reg startS2=1’b0;

reg startS3=1’b0;

reg startS4=1’b0;

reg startS5=1’b0;

reg startS6=1’b0;

reg sign0=1’b0;//S1流程控制信号

reg sign1=1’b0;

reg sign2=1’b0;

reg sign2_0=1’b0;

reg sign2_1=1’b0;

reg sign2_2=1’b0;

reg sign2_3=1’b0;

reg sign3_0=1’b0;

reg sign3_1=1’b0;

reg sign3_2=1’b0;

reg sign3_3=1’b0;

reg sign3_4=1’b0;

reg sign3_5=1’b0;

reg sign3_6=1’b0;

reg sign3_7=1’b0;

reg sign3_8=1’b0;

reg sign5_0=1’b0;

reg sign6_delay=1’b0;

reg sign6_0=1’b0;

reg sign6_1=1’b0;

reg sign6_2=1’b0;

reg sign6_3=1’b0;

reg sign6_4=1’b0;

reg sign6_5=1’b0;

reg sign6_6=1’b0;

reg sign6_7=1’b0;

reg sign6_8=1’b0;

//sha_iptop实例化

sha_iptop

CORE (

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ) );

//counter实例化

reg counter_start=0;

reg [15:0]delay=0;

reg counter_reset=0;

wire counter_stop;//counter的返回值要改为wire

wire counter_reuse;

counter c0(.clk(sha_clk),//读stop,stop=1时结束

.rst(counter_reset),

.start(counter_start),

.delay(delay),

.stop(counter_stop),

.reuse(counter_reuse));

//W32be实例化

reg w32be_start=0;

reg w32be_reset=0;

reg [31:0]w32be_data;

reg [4:0]w32be_addr;

wire [7:0]w32be_sha_wdata;

wire [1:0]w32be_pre;

wire w32be_stop;

wire w32be_reuse;

W32be W32be(

.clk(sha_clk),

.rst(w32be_reset),

.start(w32be_start),

.addr(w32be_addr),

.data(w32be_data),

.pre(w32be_pre),

.sha_wdata(w32be_sha_wdata),

.stop(w32be_stop),

.reuse(w32be_reuse));

//read实例化

reg read_start=0;

reg read_reset=0;

reg [4:0]read_addr;

wire [1:0]read_pre;

wire read_stop;

wire read_reuse;

read read(

.clk(sha_clk),

.rst(read_reset),

.start(read_start),

.addr(read_addr),

.pre(read_pre),

.stop(read_stop),

.reuse(read_reuse));

always@(posedge sha_clk)

if(sha_reset_b == 1’b0)

begin

//current_state= S1;

current_state=S0;

end

else

begin

//current_state <=next_state;

case(current_state)

S0:begin

sign0=1’b0;//重置延时标记

sign1=1’b0;

sign2=1’b0;

sha_ipen=1’b0;

sha_rw_b=1’b1;//控制读写信号开启。S2可以直接W32be了

sha_addr=5’b00000;

sha_wdata=8’b0;

pre=2’b00;

counter_start=1’b0;

delay=0;

startS1=1’b0;

current_state=S1;

end

S1:begin

if(startS1==1’b0)

begin

counter_start =1’b1;

delay =16’h0020;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h1101;

startS1=1’b1;

sign0=1’b1;

counter_reset=1;

end

end

//信号sign0,对应 #500 sha_ipen=1’b1;

else if(sign0==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

delay=16’h0019;//#50

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h1102;

sha_ipen=1’b1;

sign0=1’b0;

sign1=1’b1;

counter_reset=1;

end

end

end

//信号sign1,对应#500

else if(sign1==1’b1)

begin

counter_reset=0;

begin

counter_start=1’b1;

delay=16’h0019;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h1103;

sign1=1’b0;

current_state=S2;

counter_reset=1;

end

end

end

end

// S2:W32be(SHACTRL,32’h0000000a);#8000;

S2:begin

if(startS2==1’b0)

begin

assign pre=w32be_pre;

assign sha_wdata=w32be_sha_wdata;

sha_addr=SHACTRL;

w32be_addr=sha_addr;

/*assign 和deassign

不支持对reg 数据类型的assign或deassign进行综合,支持对wire数据类型的assign或deassign进行综合。*/

w32be_start=1’b1;

w32be_data=32’h0000000a;

// w32be_addr=SHACTRL;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

startS2=1’b1;

sign2_0=1’b1;

w32be_reset=1;

end

end

else if(sign2_0==1’b1)

begin

w32be_reset=0;

sign2_0=0;

sign2_1=1;

deassign pre;

deassign sha_wdata;

end

//信号sign2_1,对应 #8000

else if(sign2_1==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

delay=16’h0190;//#400;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h2200;

sign2_1=1’b0;

sign2_2=1’b1;

current_state=S3;

counter_reset=1;

end

end

end

end

S3:begin

//read(SHACTRL);

if(startS3==1’b0)

begin

assign pre=read_pre;

sha_rw_b=1’b1;

read_start=1’b1;

sha_addr=SHACTRL;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

startS3=1’b1;

sign3_0=1’b1;

read_reset=1;

end

end

// read(SHADO0);

else if(sign3_0==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO0;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_0=1’b0;

sign3_1=1’b1;

read_reset=1;

end

end

end

// read(SHADO1);

else if(sign3_1==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO1;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_1=1’b0;

sign3_2=1’b1;

read_reset=1;

end

end

end

// read(SHADO2);

else if(sign3_2==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO2;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_2=1’b0;

sign3_3=1’b1;

read_reset=1;

end

end

end

// read(SHADO3);

else if(sign3_3==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO3;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_3=1’b0;

sign3_4=1’b1;

read_reset=1;

end

end

end

// read(SHADO4);

else if(sign3_4==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO4;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_4=1’b0;

sign3_5=1’b1;

read_reset=1;

end

end

end

// read(SHADO5);

else if(sign3_5==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO5;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_5=1’b0;

sign3_6=1’b1;

read_reset=1;

end

end

end

// read(SHADO6);

else if(sign3_6==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO6;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_6=1’b0;

sign3_7=1’b1;

read_reset=1;

end

end

end

// read(SHADO7);

else if(sign3_7==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO7;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign3_7=1’b0;

sign3_8=1’b1;

current_state=S4;

deassign pre;

read_reset=1;

end

end

end

end

S4:

begin

if(startS4==1’b0)

begin

assign pre=w32be_pre;

assign sha_wdata=w32be_sha_wdata;

sha_rw_b=1’b1;

case(S4_state)

//W32(SHADI0,32’h61626364);

S4_1:

begin

sha_addr=SHADI0;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h61626364;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_1_2;

end

end

S4_1_2: // #100 sha_rw_b=1’b1;

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_2;

counter_reset=1;

end

end

// W32(SHADI1,32’h62636465);#100 sha_rw_b=1’b1;

S4_2:

begin

w32be_reset=0;

sha_addr=SHADI1;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h62636465;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_2_2;

end

end

S4_2_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_3;

counter_reset=1;

end

end

// W32(SHADI2,32’h63646566);

S4_3:

begin

w32be_reset=0;

sha_addr=SHADI2;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h63646566;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_3_2;

end

end

S4_3_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_4;

counter_reset=1;

end

end

// W32(SHADI3,32’h64656667);

S4_4:

begin

w32be_reset=0;

sha_addr=SHADI3;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h64656667;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_4_2;

end

end

S4_4_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_5;

counter_reset=1;

end

end

// W32(SHADI4,32’h65666768);

S4_5:

begin

w32be_reset=0;

sha_addr=SHADI4;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h65666768;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_5_2;

end

end

S4_5_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_6;

counter_reset=1;

end

end

//开始复制 W32(SHADI5,32’h66676869);

S4_6:

begin

w32be_reset=0;

sha_addr=SHADI5;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h66676869;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_6_2;

end

end

S4_6_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_7;

counter_reset=1;

end

end

// W32(SHADI6,32’h6768696a);//read(SHADI6);

S4_7:

begin

w32be_reset=0;

sha_addr=SHADI6;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6768696a;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_7_2;

end

end

S4_7_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_8;

counter_reset=1;

end

end

// W32(SHADI7,32’h68696a6b);//read(SHADI7);

S4_8:

begin

w32be_reset=0;

sha_addr=SHADI7;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h68696a6b;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_8_2;

end

end

S4_8_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_9;

counter_reset=1;

end

end

//W32(SHADI8,32’h696a6b6c);//read(SHADI8);

S4_9:

begin

w32be_reset=0;

sha_addr=SHADI8;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h696a6b6c;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_9_2;

end

end

S4_9_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_10;

counter_reset=1;

end

end

// W32(SHADI9,32’h6a6b6c6d);//read(SHADI9);

S4_10:

begin

w32be_reset=0;

sha_addr=SHADI9;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6a6b6c6d;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_10_2;

end

end

S4_10_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_11;

counter_reset=1;

end

end

// W32(SHADIA,32’h6b6c6d6e);//read(SHADIA);

S4_11:

begin

w32be_reset=0;

sha_addr=SHADIA;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6b6c6d6e;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_11_2;

end

end

S4_11_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_12;

counter_reset=1;

end

end

// W32(SHADIB,32’h6c6d6e6f);//read(SHADIB);

S4_12:

begin

w32be_reset=0;

sha_addr=SHADIB;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6c6d6e6f;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_12_2;

end

end

S4_12_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_13;

counter_reset=1;

end

end

// W32(SHADIC,32’h6d6e6f70);//read(SHADIC);

S4_13:

begin

w32be_reset=0;

sha_addr=SHADIC;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6d6e6f70;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_13_2;

end

end

S4_13_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_14;

counter_reset=1;

end

end

// W32(SHADID,32’h6e6f7071);//read(SHADID);

S4_14:

begin

w32be_reset=0;

sha_addr=SHADID;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h6e6f7071;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_14_2;

end

end

S4_14_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_15;

counter_reset=1;

end

end

// W32(SHADIE,32’h80000000);//read(SHADIE);

S4_15:

begin

w32be_reset=0;

sha_addr=SHADIE;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h80000000;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_15_2;

end

end

S4_15_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

S4_state = S4_16;

counter_reset=1;

end

end

// W32(SHADIF,32’h00000000);//read(SHADIF);

S4_16:

begin

w32be_reset=0;

sha_addr=SHADIF;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h00000000;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

S4_state=S4_16_2;

end

end

S4_16_2:

begin

counter_reset=0;

counter_start=1’b1;

delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h8888;//随便一个标示

sha_rw_b=1’b1;

//结束信号

S4_state = S4_16_2;

startS4=1;

current_state=S5;

deassign pre;

deassign sha_wdata;

counter_reset=1;

end

end

endcase

end

end

S5:

begin

if(startS5==1’b0)

begin

counter_reset=0;

counter_start =1’b1;

delay =16’h0032;//#1000ns,50个周期

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h9999;

startS5=1’b1;

sign5_0=1’b1;

counter_reset=1;

end

end

//W32(SHACTRL,32’h00000009);

else if(sign5_0==1’b1)

begin

assign pre=w32be_pre;

assign sha_wdata=w32be_sha_wdata;

sha_rw_b=1’b1;

w32be_reset=0;

sha_addr=SHACTRL;

w32be_addr=sha_addr;

w32be_start=1’b1;

w32be_data=32’h00000009;

if(w32be_stop==1)//完成延时

begin

w32be_start=1’b0;

sha_rw_b=1’b0;//控制关闭信号

w32be_reset=1;

deassign pre;

deassign sha_wdata;

sign5_0=1’b0;

current_state=S6;

end

end

end

S6:

begin

//read(SHACTRL);

if(startS6==1’b0)

begin

assign pre=read_pre;

sha_rw_b=1’b1;

read_reset=1’b0;

read_start=1’b1;

sha_addr=SHACTRL;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

startS6=1’b1;

sign6_delay=1’b1;

read_reset=1;

end

end

//#14000

if(sign6_delay==1’b1)

begin

counter_reset=0;

counter_start =1’b1;

delay =16’h02bc;//#14000ns,700个周期

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

delay=16’h9988;

sign6_delay=1’b0;

sign6_0=1’b1;

counter_reset=1;

end

end

// read(SHADO0);

else if(sign6_0==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO0;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_0=1’b0;

sign6_1=1’b1;

read_reset=1;

end

end

end

// read(SHADO1);

else if(sign6_1==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO1;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_1=1’b0;

sign6_2=1’b1;

read_reset=1;

end

end

end

// read(SHADO2);

else if(sign6_2==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO2;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_2=1’b0;

sign6_3=1’b1;

read_reset=1;

end

end

end

// read(SHADO3);

else if(sign6_3==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO3;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_3=1’b0;

sign6_4=1’b1;

read_reset=1;

end

end

end

// read(SHADO4);

else if(sign6_4==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO4;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_4=1’b0;

sign6_5=1’b1;

read_reset=1;

end

end

end

// read(SHADO5);

else if(sign6_5==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO5;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_5=1’b0;

sign6_6=1’b1;

read_reset=1;

end

end

end

// read(SHADO6);

else if(sign6_6==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO6;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_6=1’b0;

sign6_7=1’b1;

read_reset=1;

end

end

end

// read(SHADO7);

else if(sign6_7==1’b1)

begin

read_reset=0;//=1时reset

begin

read_start=1’b1;

sha_addr=SHADO7;

read_addr=sha_addr;

if(read_stop==1)//完成延时

begin

read_start=1’b0;

sign6_7=1’b0;

sign6_8=1’b1;

current_state=S7;

deassign pre;

read_reset=1;

end

end

end

end

S7:

begin

end

endcase

end

endmodule

两模块sha_read,sha_write

module W32be(clk,rst,start,addr,data,pre,sha_wdata,stop,reuse);

input clk,rst,start;//clk是给counter用的。rst是自己用的,在state.v中module state中调用复用

input [4:0] addr;

input [31:0] data;//相比较原本的那个tb(不可综合的),原来的data 8位要慢一个周期给到sha_wdata,pre也要晚一个周期传输到,感觉应该不会出问题

//原来w32be 的task中的#100都有在本文件中状态机中实现

//output,复用部分信号

output wire stop;//stop=1时,本次计时结束

output wire reuse;//resure=1时,可以开始下一次计数周期

reg stop_reg=1’b0;

reg reuse_reg=1’b0;

assign stop = stop_reg;

assign reuse = reuse_reg;

//output,正常的信号控制部分

output wire [1:0]pre;

output wire [7:0]sha_wdata;

reg [1:0]pre_reg=2’b00;

reg [7:0]sha_wdata_reg=8’b0;

assign pre=pre_reg;

assign sha_wdata=sha_wdata_reg;

//给counter的控制信号

reg counter_start=0;

reg [15:0]counter_delay=0;

reg counter_reset=0;

wire counter_stop;

wire counter_reuse;

//状态信号

reg sign0=1’b0;

reg sign1=1’b0;

reg sign2=1’b0;

reg sign3=1’b0;

reg sign4=1’b0;

reg sign5=1’b0;

reg [2:0] state=3’b000;

counter w0(.clk(clk),//读stop,stop=1时结束

.rst(counter_reset),

.start(counter_start),

.delay(counter_delay),

.stop(counter_stop),

.reuse(counter_reuse));

always @ (posedge clk or posedge rst)

begin

if (rst)//rst=1置位。正常下rst=0

begin

counter_reset=1;

stop_reg = 1’b0;

reuse_reg= 1’b1;

state = 3’b000;

counter_start=0;

end

else

begin

case(state)

3’b000:

begin

counter_reset=0;

stop_reg =1’b0;

reuse_reg=1’b1;

if(start == 1’b1)

begin

state = 3’b001;

reuse_reg=1’b0;

sign0=1;

end

else

begin

state = 3’b000;

end

end

3’b001:

begin

//#100; pre=adr; sha_wdata=data;

if(sign0==1’b1)

begin

counter_start=1’b1;

counter_delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h3201;//随便一个标示

pre_reg=2’b00;

sha_wdata_reg=data[7:0];

sign0=1’b0;

sign1=1’b1;

state = 3’b010;

counter_reset=1;

end

end

end

3’b010:

begin

//#100; pre=adr; sha_wdata=data;

if(sign1==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h3302;//随便一个标示

pre_reg=2’b01;

sha_wdata_reg=data[15:8];

sign1=1’b0;

sign2=1’b1;

counter_reset=1;

state = 3’b011;

end

end

end

end

3’b011:

begin

//#100; pre=adr; sha_wdata=data;

if(sign2==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h3203;//随便一个标示

pre_reg=2’b10;

sha_wdata_reg=data[23:16];

sign2=1’b0;

sign3=1’b1;

counter_reset=1;

state = 3’b100;

end

end

end

end

3’b100:

begin

//#100; pre=adr; sha_wdata=data;

if(sign3==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h3204;//随便一个标示

pre_reg=2’b11;

sha_wdata_reg=data[31:24];

sign3=1’b0;

sign4=1’b1;

counter_reset=1;

state = 3’b101;

end

end

end

end

3’b101:

begin

//#100; sha_rw_b=1’b0;(这个改交给module state控制,在运行w32be结束后) sha_addr=adr;(这个不用了)

if(sign4==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h3232;//随便一个标示

sign4=1’b0;

sign5=1’b1;

counter_reset=1;

state = 3’b110;

end

end

end

end

3’b110:

begin

state <=3’b111;

stop_reg <= 1’b1;

end

3’b111:

begin

state <=3’b000;

end

endcase

end

end

endmodule

module read(clk,rst,start,addr,pre,stop,reuse);

input clk,rst,start;//clk是自己用&给counter用的。rst是自己用的,在state.v中module state中调用复用

input [4:0] addr;

//output,复用部分信号

output wire stop;//stop=1时,本次计时结束

output wire reuse;//resure=1时,可以开始下一次计数周期

reg stop_reg=1’b0;

reg reuse_reg=1’b0;

assign stop = stop_reg;

assign reuse = reuse_reg;

//output,正常的信号控制部分

output wire [1:0]pre;

reg [1:0]pre_reg=2’b00;

assign pre=pre_reg;

//给counter的控制信号

reg counter_start=0;

reg [15:0]counter_delay=0;

reg counter_reset=0;

wire counter_stop;

wire counter_reuse;

//状态信号

reg sign0=1’b0;

reg sign1=1’b0;

reg sign2=1’b0;

reg sign3=1’b0;

reg sign4=1’b0;

reg sign5=1’b0;

reg [2:0] state=3’b000;

counter r0(.clk(clk),//读stop,stop=1时结束

.rst(counter_reset),

.start(counter_start),

.delay(counter_delay),

.stop(counter_stop),

.reuse(counter_reuse));

//从这开始改20160817

always @ (posedge clk or posedge rst)//rst这个项目用不上。。

begin

if (rst)//rst=1置位。正常下rst=0

begin

counter_reset<=1;

stop_reg <= 1’b0;

reuse_reg<= 1’b1;

state <= 3’b000;

counter_start<=0;

end

else

begin

case(state)

3’b000:

begin

counter_reset<=0;

stop_reg <=1’b0;

reuse_reg<=1’b1;

pre_reg=2’b00;

if(start == 1’b1)

begin

state = 3’b001;

reuse_reg=1’b0;

sign0=1;

end

else

begin

state = 3’b000;

end

end

3’b001:

begin

//#100; sha_addr=addr; pre=2’b00;

if(sign0==1’b1)

begin

counter_start=1’b1;

counter_delay=10;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h4401;//随便一个标示

pre_reg=2’b00;

sign0=1’b0;

sign1=1’b1;

state = 3’b010;

counter_reset=1;

end

end

end

3’b010:

begin

//#200; pre=2’b01;

if(sign1==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=10;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h4402;//随便一个标示

pre_reg=2’b01;

sign1=1’b0;

sign2=1’b1;

counter_reset=1;

state = 3’b011;

end

end

end

end

3’b011:

begin

// #200 pre=2’b10;//’001状态

if(sign2==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=10;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h4403;//随便一个标示

pre_reg=2’b10;

sign2=1’b0;

sign3=1’b1;

counter_reset=1;

state = 3’b100;

end

end

end

end

3’b100:

begin

// #200 pre=2’b11;

if(sign3==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=5;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h4404;//随便一个标示

pre_reg=2’b11;

sign3=1’b0;

sign4=1’b1;

counter_reset=1;

state = 3’b101;

end

end

end

end

3’b101:

begin

//#200;

if(sign4==1’b1)

begin

counter_reset=0;//=1时reset

begin

counter_start=1’b1;

counter_delay=10;

if(counter_stop==1)//完成延时

begin

counter_start=1’b0;

counter_delay=16’h4405;//随便一个标示

sign4=1’b0;

sign5=1’b1;

counter_reset=1;

state = 3’b110;

end

end

end

end

3’b110:

begin

state <=3’b111;

stop_reg <= 1’b1;

end

3’b111:

begin

state <=3’b000;

end

endcase

end

end

endmodule

计数器

module counter(clk,rst,start,delay,stop,reuse);

input clk,rst;

input start;

input [15:0] delay;//delay数据

// input delay;

output wire stop;//stop=1时,本次计时结束

output wire reuse;//resure=1时,可以开始下一次计数周期

reg [15:0] counter=16’h0;

reg stop_reg=1’b0;

reg reuse_reg=1’b0;

reg [1:0] state=2’b00;

assign stop = stop_reg;

assign reuse = reuse_reg;

always @ (posedge clk or rst)

begin

if (rst)//rst=1置位。正常下rst=0

begin

counter <= 16’h0;

stop_reg <= 1’b0;

reuse_reg<= 1’b1;

state <= 2’b00;

end

else

case(state)

2’b00:

begin

stop_reg <=1’b0;

reuse_reg<=1’b1;

if(start == 1’b1)

begin

state <= 2’b01;

reuse_reg <=1’b0;

end

else

begin

stop_reg <=1’b0;//stop=1时停止,stop=0继续

reuse_reg<=1’b1;

end

end

2’b01:

begin

counter <= counter + 1;

if(counter==delay)

begin

stop_reg <= 1’b1;//计数完毕。stop_reg=1

state <= 2’b10;

counter <=16’h0;

end

end

2’b10:

begin

// state <= 2’b11;

state <=2’b00;

end

endcase

end

endmodule

对sha_state写一个testbench做测试

/*

这个应该作为top使用

input中应该加入state中的所有信号,每次给一个就行,不要让state再去实例化这个就对了。

*/

`timescale 10ns/1ps//20ns为一个周期

module sha_state_tb;

parameter S0=3’b000,

S1=3’b001,

S2=3’b010,

S3=3’b011,

S4=3’b100,

S5=3’b101;

reg sha_clk ;

reg sha_reset_b ;

wire [7:0] sha_rdata ;

/*

reg [7:0] sha_wdata ;

reg sha_rw_b ;

reg [4:0] sha_addr ;

reg [1:0] pre ;

reg sha_ipen ;

*/

// wire monitor1,monitor2,monitor3;

/*

reg delaystart=0;

reg delaystop=0;//读的延时返回信息,stop=1时计数停止/delay完成,开始下一步

reg [15:0]delay=1;

*/

sha_state

sha_state(

.sha_clk (sha_clk ) ,

.sha_rdata (sha_rdata ) ,

.sha_reset_b (sha_reset_b ),

/*

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_ipen (sha_ipen ) ,

*/

.monitor1(monitor1),

.monitor2(monitor2),

.monitor3(monitor3));

/*

sha_state

DUT(

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ));

*/

/* .delaystart(delaystart), 应该不用给计数器的控制信号,在sha_state module中自己定义

.delaystop(delaystop),

.delay(delay));

*/

initial begin

sha_clk = 1’b0;

forever

#1 sha_clk = ~sha_clk ;

end

initial begin

sha_reset_b=1’b1;

#25 sha_reset_b=1’b0;

#25 sha_reset_b=1’b0;

#25 sha_reset_b=1’b1;

/*

#1000000;

$stop;

*/

end

endmodule

/*

CTRL DUT0 (

.clk(sys_clk),

.reset(sys_reset),

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ),

.stop(stop),

.busy(busy));

SHA_IP DUT1 (

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ));

always #10 sys_clk = ~sys_clk;

initial

begin

sys_clk = 0;

sys_reset = 0;

#10000000;

$stop;

end

endmodule

*/

需要补充的几点是:

ü Sha_state_tb对所有sha_state的input信号的调用设为reg,所有sha_state的output设为wire,tb文件本身没有输入输出

ü assign 和deassign 不支持对reg 数据类型的assign或deassign进行综合,支持对wire数据类型的assign或deassign进行综合。

ü counter,w32be和read的reuse控制还是没有用到。当时的想法是留着吧,也许后面有用

出的波形

我的芯片之路4

 

W32开始时

我的芯片之路4

 

我的芯片之路4
我的芯片之路4
我的芯片之路4

 

READ开始

可以看到read的图rdata出现 85 6a 09 e6(见前文算法出来的数),和预期一致。

至此与原无法综合的tb文件完成结果一致,前仿完成

下期将开始综合和后仿

——————————–

微博@georgeuser,一枚很可能要搞硬件的喵控的专业记录日记。

记录我所走过的路,愿我的分享能予人一些借鉴,也愿我某日再回头时能再拾起细节。