我的芯片之路1

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我的芯片之路1

回所后第一个任务是给一个采用sha算法芯片做测试,有综合后的sha芯片代码(仿真用),和一个比较粗糙的testbench,我的任务是将testbench改成可以综合的代码然后写入FPGA中给一块实际的sha芯片做测试。

这块芯片是将输入的数据做算法加密,在sha_rdata8位8位的读出,核心芯片是32位的,加了写入时和读出时的32->8位的壳

当我写入FPGA和芯片连接在一起后,分析仪显示出仿真时结果,即完成任务&芯片正常

———————————–

原tb代码如下(略作修改,使数据顺序准确了些)

`timescale 1ns/1ps

module sha_iptop_tb ;

reg [7:0] sha_wdata ; //与输入端口相连接的变量定义为reg

reg sha_rw_b ;

reg sha_clk ;

reg [4:0] sha_addr ;

reg [1:0] pre ;

wire [7:0] sha_rdata ; //与输出端口相连的定义为wire

reg sha_ipen ;

reg sha_reset_b ;

parameter SHACTRL=5’b01000,

SHADI0=5’b10000,

SHADI1=5’b10001,

SHADI2=5’b10010,

SHADI3=5’b10011,

SHADI4=5’b10100,

SHADI5=5’b10101,

SHADI6=5’b10110,

SHADI7=5’b10111,

SHADI8=5’b11000,

SHADI9=5’b11001,

SHADIA=5’b11010,

SHADIB=5’b11011,

SHADIC=5’b11100,

SHADID=5’b11101,

SHADIE=5’b11110,

SHADIF=5’b11111,

SHADO0=5’b00000,

SHADO1=5’b00001,

SHADO2=5’b00010,

SHADO3=5’b00011,

SHADO4=5’b00100,

SHADO5=5’b00101,

SHADO6=5’b00110,

SHADO7=5’b00111;

sha_iptop

DUT (

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ) );

// initial $sdf_annotate (“sha_iptop.sdf”,DUT);

initial begin

sha_clk = 1’b0;

forever

#100 sha_clk = ~sha_clk ;

end

initial begin

sha_ipen=1’b0;

sha_rw_b=1’b1;

sha_addr=5’b00000;

sha_wdata=8’b0;

sha_reset_b=1’b1;

pre=2’b00; //add

#500 sha_reset_b=1’b0;

#500 sha_reset_b=1’b1;

#500 sha_ipen=1’b1;

#500;

//????????????????????sha0??

@(posedge sha_clk);

W32be(SHACTRL,32’h0000000a);

#8000;

read(SHACTRL);

read(SHADO0);

read(SHADO1);

read(SHADO2);

read(SHADO3);

read(SHADO4);

read(SHADO5);

read(SHADO6);

read(SHADO7);

//???????

W32(SHADI0,32’h61626364);

//read(SHADI0);

W32(SHADI1,32’h62636465);

//read(SHADI1);

W32(SHADI2,32’h63646566);

//read(SHADI2);

W32(SHADI3,32’h64656667);//read(SHADI3);

W32(SHADI4,32’h65666768);//read(SHADI4);

W32(SHADI5,32’h66676869);//read(SHADI5);

W32(SHADI6,32’h6768696a);//read(SHADI6);

W32(SHADI7,32’h68696a6b);//read(SHADI7);

W32(SHADI8,32’h696a6b6c);//read(SHADI8);

W32(SHADI9,32’h6a6b6c6d);//read(SHADI9);

W32(SHADIA,32’h6b6c6d6e);//read(SHADIA);

W32(SHADIB,32’h6c6d6e6f);//read(SHADIB);

W32(SHADIC,32’h6d6e6f70);//read(SHADIC);

W32(SHADID,32’h6e6f7071);//read(SHADID);

W32(SHADIE,32’h80000000);//read(SHADIE);

W32(SHADIF,32’h00000000);//read(SHADIF);

/*

read(SHADI0);

read(SHADI1);

read(SHADI2);

read(SHADI3);

read(SHADI4);

read(SHADI5);

read(SHADI6);

read(SHADI7);

read(SHADI8);

read(SHADI9);

read(SHADIA);

read(SHADIB);

read(SHADIC);

read(SHADID);

read(SHADIE);

read(SHADIF);

*/

//????

read(SHACTRL);

W32(SHACTRL,32’h00000009);

read(SHACTRL);

#14000;

read(SHADO0);

read(SHADO1);

read(SHADO2);

read(SHADO3);

read(SHADO4);

read(SHADO5);

read(SHADO6);

read(SHADO7);

read(SHACTRL);

end

task W32(input [4:0] adr,input [31:0] data );

begin

W8(2’b00,data[7:0]);

W8(2’b01,data[15:8]);

W8(2’b10,data[23:16]);

W8(2’b11,data[31:24]);

#100;

sha_rw_b=1’b0;

sha_addr=adr;

@(posedge sha_clk);

#100 sha_rw_b=1’b1;

end

endtask

task W32be(input [4:0] adr,input [31:0] data );

begin

W8(2’b00,data[7:0]);

W8(2’b01,data[15:8]);

W8(2’b10,data[23:16]);

W8(2’b11,data[31:24]);

#100;

sha_rw_b=1’b0;

sha_addr=adr;

@(posedge sha_clk);

//#5 sha_rw_b=1’b1;

end

endtask

task W8(input [1:0] adr,input [7:0] data );

begin

#100;

pre=adr;

sha_wdata=data;

@(posedge sha_clk);

end

endtask

task read( input [4:0] adr );

begin

#100;

sha_wdata=8’b0;

sha_rw_b=1’b1;

sha_addr=adr;

pre=2’b00;//试试

@(posedge sha_clk);

#200 pre=2’b00;

#200 pre=2’b01;

#200 pre=2’b10;

#200 pre=2’b11;

#200;

end

endtask

在modelsimse10.2c波形如下

 

我的芯片之路1
我的芯片之路1
我的芯片之路1

 

// 1.SHACTRL-MODE = 10; SHACTRL-INIT = 1;

// 2.Input Data

// SHADI

W32(SHADI0,0x61626364);

W32(SHADI1,0x62636465);

W32(SHADI2,0x63646566);

W32(SHADI3,0x64656667);

W32(SHADI4,0x65666768);

W32(SHADI5,0x66676869);

W32(SHADI6,0x6768696a);

W32(SHADI7,0x68696a6b);

W32(SHADI8,0x696a6b6c);

W32(SHADI9,0x6a6b6c6d);

W32(SHADIA,0x6b6c6d6e);

W32(SHADIB,0x6c6d6e6f);

W32(SHADIC,0x6d6e6f70);

W32(SHADID,0x6e6f7071);

W32(SHADIE,0x80000000);

W32(SHADIF,0x00000000);

// 3.SHACTRL-START = 1;

// 4. Read SHACTRL-BUSY = 0

// 5. Read Result

// SHADO Standard Data

SHADO0 = 0x85e655d6;

SHADO1 = 0x417a1795;

SHADO2 = 0x3363376a;

SHADO3 = 0x624cde5c;

SHADO4 = 0x76e09589;

SHADO5 = 0xcac5f811;

SHADO6 = 0xcc4b32c1;

SHADO7 = 0xf20e533a;

测试依据如上,标红的数据即上图sha_wdata和sha_rdata数据

————————————————

然后开始修改之路

【2016.7】我的第一个想法,是将源代码类似C++式的修改,将延时能硬件综合化。//这个想法是十分外行的,不具有硬件思维,被批的挺惨的

*****版本shasha3——20160809*****

module sha_iptop_tb ;

reg [7:0] sha_wdata ; //与输入端口相连接的变量定义为reg

reg sha_rw_b ;

reg sha_clk ;

reg [4:0] sha_addr ;

reg [1:0] pre ;

wire [7:0] sha_rdata ; //与输出端口相连的定义为wire

reg sha_ipen ;

reg sha_reset_b ;

integer i=0;

parameter SHACTRL=5’b01000,

SHADI0=5’b10000,

SHADI1=5’b10001,

SHADI2=5’b10010,

SHADI3=5’b10011,

SHADI4=5’b10100,

SHADI5=5’b10101,

SHADI6=5’b10110,

SHADI7=5’b10111,

SHADI8=5’b11000,

SHADI9=5’b11001,

SHADIA=5’b11010,

SHADIB=5’b11011,

SHADIC=5’b11100,

SHADID=5’b11101,

SHADIE=5’b11110,

SHADIF=5’b11111,

SHADO0=5’b00000,

SHADO1=5’b00001,

SHADO2=5’b00010,

SHADO3=5’b00011,

SHADO4=5’b00100,

SHADO5=5’b00101,

SHADO6=5’b00110,

SHADO7=5’b00111;

sha_iptop

DUT (

.sha_wdata (sha_wdata ) ,

.sha_rw_b (sha_rw_b ) ,

.sha_clk (sha_clk ) ,

.sha_addr (sha_addr ) ,

.pre (pre ) ,

.sha_rdata (sha_rdata ) ,

.sha_ipen (sha_ipen ) ,

.sha_reset_b (sha_reset_b ) );

always @(negedge sha_reset_b ) //reset

begin

sha_ipen=1’b0;

sha_rw_b=1’b1;

sha_addr=5’b00000;

sha_wdata=8’b0;

sha_reset_b=1’b1;

pre=2’b00; //add

for(i = 0; i < 25; i = i + 1)

begin

end

sha_reset_b=1’b0;

for(i = 0; i < 25; i = i + 1)

begin

end

sha_reset_b=1’b1;

for(i = 0; i < 25; i = i + 1)

begin

end

sha_ipen=1’b1;

for(i = 0; i < 25; i = i + 1)

begin

end

end

always @(posedge sha_clk ) //initialize&运作

begin

if(sha_reset_b==1)//正常工作

begin

W32be(SHACTRL,32’h0000000a);

for(i = 0; i < 320; i = i + 1)

begin

end

read(SHACTRL);

read(SHADO0);

read(SHADO1);

read(SHADO2);

read(SHADO3);

read(SHADO4);

read(SHADO5);

read(SHADO6);

read(SHADO7);

read(SHADI0);

read(SHADI1);

read(SHADI2);

read(SHADI3);

read(SHADI4);

read(SHADI5);

read(SHADI6);

read(SHADI7);

read(SHADI8);

read(SHADI9);

read(SHADIA);

read(SHADIB);

read(SHADIC);

read(SHADID);

read(SHADIE);

read(SHADIF);

//???????

W32(SHADI0,32’h61626364);

//read(SHADI0);

W32(SHADI1,32’h62636465);

//read(SHADI1);

W32(SHADI2,32’h63646566);

//read(SHADI2);

W32(SHADI3,32’h64656667);//read(SHADI3);

W32(SHADI4,32’h65666768);//read(SHADI4);

W32(SHADI5,32’h66676869);//read(SHADI5);

W32(SHADI6,32’h6768696a);//read(SHADI6);

W32(SHADI7,32’h68696a6b);//read(SHADI7);

W32(SHADI8,32’h696a6b6c);//read(SHADI8);

W32(SHADI9,32’h6a6b6c6d);//read(SHADI9);

W32(SHADIA,32’h6b6c6d6e);//read(SHADIA);

W32(SHADIB,32’h6c6d6e6f);//read(SHADIB);

W32(SHADIC,32’h6d6e6f70);//read(SHADIC);

W32(SHADID,32’h6e6f7071);//read(SHADID);

W32(SHADIE,32’h80000000);//read(SHADIE);

W32(SHADIF,32’h00000000);//read(SHADIF);

read(SHADI0);

read(SHADI1);

read(SHADI2);

read(SHADI3);

read(SHADI4);

read(SHADI5);

read(SHADI6);

read(SHADI7);

read(SHADI8);

read(SHADI9);

read(SHADIA);

read(SHADIB);

read(SHADIC);

read(SHADID);

read(SHADIE);

read(SHADIF);

read(SHACTRL);

W32(SHACTRL,32’h00000009);

read(SHACTRL);

for(i = 0; i < 560; i = i + 1)

begin

end

read(SHADO0);

read(SHADO1);

read(SHADO2);

read(SHADO3);

read(SHADO4);

read(SHADO5);

read(SHADO6);

read(SHADO7);

read(SHACTRL);

end

else

begin

end

end

task W32(input [4:0] adr,input [31:0] data );

begin

W8(2’b00,data[7:0]);

W8(2’b01,data[15:8]);

W8(2’b10,data[23:16]);

W8(2’b11,data[31:24]);

for(i = 0; i < 4; i = i + 1)

begin

end

sha_rw_b=1’b0;

sha_addr=adr;

@(posedge sha_clk);

for(i = 0; i < 4; i = i + 1)

begin

end

sha_rw_b=1’b1;

end

endtask

task W32be(input [4:0] adr,input [31:0] data );

begin

W8(2’b00,data[7:0]);

W8(2’b01,data[15:8]);

W8(2’b10,data[23:16]);

W8(2’b11,data[31:24]);

for(i = 0; i < 4; i = i + 1)

begin

end

sha_rw_b=1’b0;

sha_addr=adr;

@(posedge sha_clk);

//#5 sha_rw_b=1’b1;

end

endtask

task W8(input [1:0] adr,input [7:0] data );

begin

for(i = 0; i < 4; i = i + 1)

begin

end

pre=adr;

sha_wdata=data;

@(posedge sha_clk);

end

endtask

task read( input [4:0] adr );

begin

for(i = 0; i < 4; i = i + 1)

begin

end

sha_wdata=8’b0;

sha_rw_b=1’b1;

sha_addr=adr;

pre=2’b00;//试试

@(posedge sha_clk);

for(i = 0; i < 8; i = i + 1)

begin

end

pre=2’b00;

for(i = 0; i < 8; i = i + 1)

begin

end

pre=2’b01;

for(i = 0; i < 8; i = i + 1)

begin

end

pre=2’b10;

for(i = 0; i < 8; i = i + 1)

begin

end

pre=2’b11;

for(i = 0; i < 8; i = i + 1)

begin

end

end

endtask

endmodule

这个是试图利用for循环做延时。问题很多,回头看是很不成熟的想法,典型的用软件思维套硬件。

自然仿真结果也是完全不对的。

我所做的东西到底怎么和shaip芯片链接呢?连线是如何定义的?定义为reg还是wire?

我需要为shaip提供什么信号?

我开始思考这些问题,也得到老师的提示(主要是老师的提示)

找到shaip芯片的sha_iptop module去看信号的定义和细节。

module sha_iptop ( sha_clk, sha_reset_b, sha_wdata, sha_addr, sha_rw_b,

sha_ipen, sha_rdata, pre );

input [7:0] sha_wdata;

input [4:0] sha_addr;

output [7:0] sha_rdata;

input [1:0] pre;

input sha_clk, sha_reset_b, sha_rw_b, sha_ipen;

wire [31:0] w_dataout;

wire [31:0] w_sha_rdata;

p8to32 DUT ( .sha_clk(sha_clk), .sha_reset_b(sha_reset_b), .pre(pre),

.datain(sha_wdata), .dataout(w_dataout) );

sha_ip sha_ip ( .sha_clk(sha_clk), .sha_reset_b(sha_reset_b), .sha_wdata(

w_dataout), .sha_addr(sha_addr), .sha_rw_b(sha_rw_b), .sha_ipen(

sha_ipen), .sha_rdata(w_sha_rdata) );

p32to8 p32to8 ( .pre(pre), .datain(w_sha_rdata), .dataout(sha_rdata) );

endmodule

捋一捋信号,一共sha_clk, sha_reset_b, sha_wdata, sha_addr, sha_rw_b, sha_ipen, sha_rdata, pre几个

sha_clk, 时钟

sha_reset_b复位

sha_wdata写入的8位数据,常量

,sha_addr, 写入数据的地址

sha_rw_b, 读写线控制信号

sha_ipen, 使能信号

sha_rdata,读出的7位数据/唯一输出

pre,32转8的一个控制信号(这个信号的做法有待商榷,不过不讨论了)

 

微博@georgeuser,一枚很可能要搞硬件的喵控的专业记录日记。

记录我所走过的路,愿我的分享能予人一些借鉴,也愿我某日再回头时能再拾起细节。